IC Design Tips, where IC Design Issues are Explained and Solved

This article explains in detail why two-FF synchronizers can help prevent metastability from propagating and resolve CDC issues in digital IC design . As explained in this article , the main problem with Clock Domain Crossing ( CDC ) is metastability due to setup or hold time violations of asynchronous crossing signals when capturing by the destination clock domain, in which the metastable state can propagate throughout the design causing data loss and even chip malfunction. Metastability in CDC design is not preventable, but synchronizers can be employed to avoid the propagation of the metastable state; hence, prevent system failures. How can two-FF synchronizers prevent metastability from propagating? As explained in this article and also shown in the waveform above, when the first  flip-flop (FF) data input violates the setup or hold time requirements, the output A/B becomes metastable. However, after an unpredictable delay (Tco), the FF output would settle to a stable ...

CDC is an abbreviation of Clock Domain Crossing , which is one of the most critical issues in digital IC design when there are multiple asynchronous clock domains in the chips and signals are crossed from one clock domain to another. What are CDC issues when crossing signals between asynchronous clock domains? Synchronous clocks show constant phase relationships, whereas asynchronous clocks exhibit variable phase and time relationships. Thus, when a signal crosses between two asynchronous clock domains,  there are likely setup or hold time violations at the destination flip-flop . This would cause metastability , hence resulting in metastability propagation and data loss in the destination clock domain as shown in the following waveform. To read more about setup time , hold time , and metastability , check here . How do we avoid the CDC metastability issue? The answer is NO. We cannot avoid metastability or timing violations when crossing between asynchronous clock domains since...

This article explained the setup and hold time slack for different timing paths in digital IC design , following the setup and hold time equations explanation in the last posts . Credit: Cadence Design Systems The figure above shows the most common timing path, register-to-register. The launching clock triggers the data into the first flip-flop and the capture clock captures the data, which saves the data into the receiving flip-flop. However, to reliably save the data into the flip-flop, the arrival time of the data required to meet the setup and hold time requirements of the flip-flop as explained in this post . Setup and hold slack is defined as the difference between the required time (based on setup and hold time) and the arrival time of the data at the endpoint. The slack value is used by STA tools to identify the violated timing paths for further optimization to satisfy the setup and hold timing. Setup Slack = Required Time - Arrival Time Hold Slack  = Arrival Time...

This article explained all the hold time equations for different timing paths in digital IC design . Hold time is the minimum time duration that the input data required to be stable AFTER the active clock edge so that the input data can be reliably saved into the flip-flop . Read more about hold time: here . There are 3 main timing paths that require setup time constraints as described in the following figure: register-to-register, input-to-register, and register-to-output. Credit: Cadence Design Systems Hold Time Equation for Register-To-Register Timing Paths Credit: Cadence Design Systems Required Time = Hold Time (of the capturing flip-flop, from the timing .lib) Arrival Time = CK→Q Delay (of Launching flip-flop) + Comb. Delay To meet hold time constraints, Arrival Time ⋝ Required Time, meaning that data required to arrive (stable) at the next flip-flop after the hold time window. =>  CK→Q Delay (of Launching flip-flop) + Comb. Delay ⋝ Hold Time => Hold Time ≤ CK→Q D...

 Last time, we described the reasons  why setup and hold time are required in digital IC design . This article explained all the setup time equations and requirements for different timing paths in the digital IC design.  Setup time  is the minimum time duration that the input data D required to be stable before the active clock edge so that the input data can be stored correctly into the  flip-flop . Read more about setup time:  here . There are 3 main timing paths that require setup time constraints as shown below: register-to-register, input-to-register, and register-to-output. Credit: Cadence Design Systems Setup Time Equation for Register-To-Register Timing Paths Most of the timing paths inside the chip are register -to-register. Setup time constraints ensure that the signal (Q) launched by the first flip-flop does not arrive too late so that the second flip-flop can capture it correctly. Setup time equation for the reg-to-reg path: Required Time = ...

This article provides tips on how to fix setup time violations manually with ECO after Innovus failed to fix all the setup time violations automatically at the post_route step.  What is Setup Time Violation? Setup time violation occurs when the flip-flop input data failed to meet the setup time requirement . In other words, flip-flop input data is not stable or changed during the setup time (tsu) window. Metastability might occur when the setup time (tsu) is violated and it takes an unpredictable delay (tco) for the flip-flop's state to settle as shown in the timing diagram below. If the flip-flop state failed to settle to a logic low or high when reaching the next flip-flops, the metastable states can be propagated to the whole chip and it can cause system failures. Data lost might be observed even if the metastable state is settled back to a valid state (old data) when capturing by the next flip-flops. Check here for setup time constraints and equations Credit: Intel Altera Re...

This tutorial not only describes the concept of setup and hold time, but also explains why setup and hold time are required in digital IC design. Flip-Flop 's Setup and hold time are also one of the most common interview questions for IC design engineers. To facilitate the understanding of setup and hold time , it is recommended to check out the explanation of flip-flop schematic and how it works: here  What is Setup Time? Setup time is the required time duration that the input data MUST be stable before the triggering-edge of the clock. If data is changing within this setup time window, the input data might be lost and not stored in the flip-flop as metastability  might occur. What is metastability? When setup and hold time requirements are violated, the flip-flop state becomes unstable, and after an unpredictable duration, the state of the flip-flop can settle either way (1 or 0). This scenario is known as metastability. As shown in the following diagram, output Q1 passes ...

This tutorial explained in detail everything inside the flip-flop, a fundamental building block in digital IC design, including the flip-flop's schematic and how it works. Why Flip-Flop Understanding is Needed? Flip-flop , which is typically used for data storage ( D-type Flip-Flop ), is one of the most critical components in any digital system. Understanding flip-flops will help designers understand the  setup and hold time concepts, which are two of the most critical timing requirements that all the digital chips should meet before sending out for fabrication. Flip-flop's setup and hold time are also one of the most common interview questions for IC design engineers. RTL code to infer Flip-Flop in digital IC design:  Verilog ,  VHDL Below is a typical architecture of any sequential systems in digital IC/FPGA design involving 2 flip-flops (highlighted in red color) and the combinational logic. Many flip-flops together form register banks. In microcontroller chips, reg...